A liquid crystal display apparatus for use in mobile telephone terminal or the like uses, for the purpose of displaying a video signal, a video processing circuit which processes a video signal by digital signal processing (See Japanese Patent Application Laid-Open Gazette No. 2000-330520 for instance). FIG. 4 shows a conventional video processing circuit 13 which is used in a mobile telephone terminal.
The video processing circuit 13 comprises a latch circuit 3 and a GRAM (graphics Random access memory) 2. The GRAM 2 is a readable/writable memory which stores pixel data amounting to one screen displayed by a display panel 8, and in this memory, pixel data corresponding to one pixel which forms the display panel 8 is written in synchronization to a memory clock signal 12 which is input.
The latch circuit 3 is a circuit which reads from the GRAM 2 pixel data equivalent to one scanning line displayed by the display panel 8 and which stores the same.
An operation of such a conventional video processing circuit 13 will now be described.
A data latch signal 10 is input to the latch circuit 3. Meanwhile, a display read control signal 9 and the memory clock signal 12 are input to the GRAM 2.
FIG. 5 is a timing chart of these various types of drive signals and the control signal to the video processing circuit 13.
In the timing chart in FIG. 5, the display read control signal 9 shown in FIG. 4 is shown as a display read control signal 51, the data latch signal 10 shown in FIG. 4 is shown as a data latch signal 52, and the memory clock signal 12 shown in FIG. 4 is shown as a memory clock signal 53. Further, in FIG. 5, display data 54 and display data 55 are output data from the GRAM 2 corresponding to the bits of memory elements which form the GRAM 2, of which the display data 54 is data output from the GRAM 2 corresponding to a bit of a memory element forming the GRAM 2 when this bit is set to the L-state from the H-state while the display data 55 is data output from the GRAM 2 corresponding to a bit of a memory element forming the GRAM 2 when this bit is set to the H-state from the L-state. At each bit of the memory elements forming the GRAM 2, one bit of pixel data to be displayed is stored.
The display read control signal 51 is a control signal which can be in the H (High)-state which is indicative of a discharge period and the L (Low)-state which is indicative of a memory update period. When the display read control signal 51 fed to the GRAM 2 is in the H-state, that is, the discharge period, all of display data from the GRAM 2 is in the L-state regardless of whether the bits of the memory elements which form the GRAM 2 corresponding to this display data are in the L-state or the H-state. When the display read control signal 51 fed to the GRAM 2 is in the L-state, that is, the memory update period, the latch circuit 3 reads from the GRAM 2 pixel data equivalent to one scanning line and stores the same.
However, the display data output from the GRAM 2, once set to the H-state during the memory update period, remains in the H-state during the memory update period independently of the values of the bits of the memory elements which form the GRAM 2. The display data output from the GRAM 2 can return to the L-state only after the display read control signal 51 has switched to the H-state, that is, the discharge period. In other words, the display data output from the GRAM 2 enters the L-state as soon as the display read control signal 51 switches to the H-state, even without the L-state written at the bits of the memory elements which form the GRAM 2. This is the characteristic of display data output from the GRAM 2.
Further, when the data latch signal 52 is fed to the latch circuit 3, the latch circuit 3 finalizes the values of the bits of memory elements which form the latch circuit 3 in response to falling of the data latch signal 52.
Further, when pixel data are written in the GRAM 2, the memory clock signal 53 is fed to the GRAM 2 and the memory clock signal 53 falls. In this manner, the pixel data are written in the GRAM 2 in synchronization to the memory clock signal 53.
Writing of the pixel data in the GRAM 2 takes place independently of reading of pixel data equivalent to one scanning line from the GRAM 2 to the latch circuit 3.
This operation is summarized as follows.
That is, while the display read control signal 51 remains in the H-state, the display data output from the GRAM 2 becomes the L-state. Upon inputting of the memory clock signal to the GRAM 2, the pixel data is written in the GRAM 2 at falling of the memory clock signal.
As the display read control signal 51 changes to the L-state from the H-state, i.e., as the display read control signal 51 enters the memory update period, the latch circuit 3 reads the pixel data equivalent to one scanning line stored in the GRAM 2 into the respective memory elements which form the latch circuit 3 and stores the pixel data in the respective memory elements.
After inputting of the data latch signal 52 to the latch circuit 3, the latch circuit 3 finalizes the pixel data equivalent to one scanning line read and stored into the memory elements when the data latch signal 52 falls.
When display data output from the GRAM 2 is updated to the L-state from the H-state as in the case of the display data 54 for example, the latch circuit 3 sets the corresponding memory elements of the latch circuit 3 to the L-state in response to falling of the data latch signal 52.
On the contrary, when display data output from the GRAM 2 is updated to the H-state from the L-state as in the case of the display data 55 for example, the latch circuit 3 sets the corresponding memory elements of the latch circuit 3 to the H-state in response to falling of the data latch signal 52.